1. Field of the Invention
The present invention relates to a JTAG device having an IP (intellectual property) core.
2. Description of the Related Art
A JTAG device is an integrated circuit conforming to a standard developed by the Joint Test Action Group (JTAG) to simplify the testing of integrated circuits and printed circuit boards. This standard, which has been adopted as standard 1149.1 (Standard Test Access Port and Boundary-Scan Architecture) of the Institute of Electrical and Electronics Engineers (IEEE), defines a boundary scan technique that is widely used in the semiconductor industry.
As an example of a conventional JTAG device, FIG. 10 schematically shows an integrated circuit including a flash controller 101 as an IP core, a flash memory 102, and a boundary scan circuit for testing the flash controller 101. The boundary scan circuit includes a boundary scan register (BSR), a test access port (TAP), and a TAP interface (TAP IF). The boundary scan register includes a pair of input boundary scan cells (BSC1, BSC2) and a pair of output boundary scan cells (BSC3, BSC4). The test access port includes a Test Data In (TDI) terminal, a Test Clock (TCK) terminal, a Test Mode Select (TMS) terminal, and a Test Data Out (TDO) terminal.
The TDI, TCK, and TMS terminals are coupled to input terminals of the TAP interface. The TDI terminal is also coupled to a serial data input terminal (SI) of input boundary scan cell BSC1. The TDO terminal is coupled to a serial data output (SO) terminal of output boundary scan cell BSC4 and an output terminal of the TAP interface. Data output (DO) terminals of the input boundary scan cells BSC1 and BSC2 are coupled to input terminals of the flash controller 101. Output terminals of the flash controller 101 are coupled to data input (DI) terminals of the output boundary scan cells BSC3 and BSC4. The DO terminals of the output boundary scan cells BSC3 and BSC4 are coupled to input terminals of the flash memory 102. The SO terminal of input boundary scan cell BSC1 is coupled to the SI terminal of input boundary scan cell BSC2. The SO terminal of input boundary scan cell BSC2 is coupled to the SI terminal of output boundary scan cell BSC3. The SO terminal of output boundary scan cell BSC3 is coupled to the SI terminal of output boundary scan cell BSC4.
FIG. 11 is a circuit diagram of a conventional output boundary scan cell. The output boundary scan cell includes an input multiplexer MUX1, an output multiplexer MUX2, a shift flip-flop FF1, and a latch flip-flop FF2. The output boundary scan cell further includes the DI, DO, SI, and SO terminals mentioned above, and terminals for input of a shift select signal (Shift-DR), a data shift clock signal (Clock-DR), a data latch clock signal (Update-DR), and a mode select signal (Mode).
The DI terminal is coupled to input terminal A of multiplexers MUX1 and MUX2. The SI terminal is coupled to input terminal B of the input multiplexer MUX1. The output terminal Y of the input multiplexer MUX 1 is coupled to the data input terminal D of the shift flip-flop FF1. The data output terminal Q of the shift flip-flop FF1 is coupled to the SO terminal and the data input terminal D of the latch flip-flop FF2. The data output terminal Q of the latch flip-flop FF2 is coupled to data input terminal B of the output multiplexer MUX2. The data output terminal Y of the output multiplexer MUX2 is coupled to the DO terminal. The Shift-DR signal is supplied to the selection input terminal S of the input multiplexer MUX1. The Clock-DR signal is supplied to the clock input terminal (CK) of the shift flip-flop FF1. The Update-DR signal is supplied to the CK terminal of the latch flip-flop FF2. The Mode signal is supplied to the S terminal of the output multiplexer MUX2.
FIG. 12 is a block diagram showing the configuration of a conventional TAP interface (TAP IF). The TAP interface includes a TAP controller (TAPC), an instruction register (IR), an instruction decoder (ID), a multiplexer (MUX), and an output buffer (BUF). The configuration of the TAP controller and its control method conform to the above-mentioned IEEE standard 1149.1.
The conventional procedure for testing the flash controller 101 will be briefly described below.
The TAP controller is a state machine with a CAPTURE-DR state, a SHIFT-DR state, an UPDATE-DR state, a SHIFT-IR state, an UPDATE-IR state, and various other states. State transitions are controlled by the TCK and TMS signals during the test procedure. Test instruction codes (INTEST etc.) input from the TDI terminal are shifted into the instruction register IR in the SHIFT-IR state, and passed to the instruction decoder ID in the UPDATE-IR state.
In the SHIFT-DR state, the Shift-DR signal selects the SI input terminals of the boundary scan cells, and test data input from the TDI terminal are shifted into the shift flip-flops FF1 of the input boundary scan cells BSCI in response to the Clock-DR signal. In the UPDATE-DR state, the test data are transferred from the shift flip-flops FF1 to the latch flip-flops FF2 and output to the flash controller 101 through the output multiplexers MUX2 and DO terminals of the input boundary scan cells BSCI, in response to the Update-DR and Mode signals. An internal test of the flash controller 101 then begins.
The output data of the flash controller 101 resulting from the test are captured by the shift flip-flops FF1 of the output boundary scan cells in the CAPTURE-DR state, in which the Shift-DR signal selects input terminal A of the input multiplexers MUX1. The captured output data are then shifted through the shift flip-flops FF1 and output serially from the TDO terminal in the SHIFT-DR state, the Shift-DR signal once more selecting input terminal B of the input multiplexers MUX1.
A problem that arises during this test procedure is that each time test data are output from the input boundary scan cells BSCI to the flash controller 101, data are also output from the output boundary scan cells BSCO to the flash memory 102. This is inconvenient, because the data output to the flash memory 102 can have undesired consequences, such causing an unintended write or erase operation in the flash memory 102. These consequences can be avoided by supplying predetermined data for the output boundary scan cells BSCO before supplying test data for the input boundary scan cells BSCI to the TDI terminal, but that lengthens the test time.
Furthermore, the unwanted output of data from the output boundary scan cells BSCO to the flash memory 102 makes it difficult to test the flash controller 101 and the flash memory 102 together. The flash controller 101 and the flash memory 102 must accordingly be tested separately, which takes still more time.
FIG. 13 is a timing diagram of the clock signals in a conventional JTAG device. In the conventional JTAG device, the system clock signal CLK that drives the flash controller 101 and the Clock-DR signal supplied to the CK terminals of the shift flip-flops FF1 of the boundary scan cells BSCI and BSCO are derived from different clock trees. The timing of the Clock-DR signal must be adjusted with respect to the timing of the system clock signal CLK by an amount tA that provides an adequate set-up time tS and hold time tH with respect to the data input (D) to the shift flip-flop FF1. At high clock speeds, this adjustment is difficult. The IP core must therefore be tested at a comparatively low clock speed, which also increases the test time.